1. Field of the Invention
The present invention relates to a method of forming a barrier layer, and more particularly, to a method, which includes an examination procedure and a rework procedure, to form the barrier layer effectively and economically.
2. Description of the Prior Art
Particles are nearly inevitable in semiconductor processes due to many reasons. These particles influence the electrical property of semiconductor elements formed in wafers. If the electrical property is not acceptable, an entire batch of wafers must be discarded. This indeed increases the production cost of semiconductor components. Normally, a wet etching process or a liquid type scrubber machine is adopted for removing the particles. However, these methods only remove the particles that adhere to the surface of the wafer. Once the particles are formed with the film during the deposition process or if the particles exist on the surface of the film formed previously, these methods fail to get rid of the particles. This seriously affects the yield of semiconductor processes.
In addition, as the critical dimension reduces while the component integrity improves in semiconductor processes, physical vapor deposition (PVD) technologies, such as evaporation or sputtering, are no longer available to fulfill the requirements of the modern semiconductor processes, especially when the critical dimension is less or the aspect ratio is higher. Therefore, for obtaining a better step coverage, the chemical vapor deposition (CVD) technology is normally adopted to form a thin film with a better shape.
Though a film with better step coverage is easy to be obtained by CVD technology, particles tend to occur in the film made by CVD process due to some inevitable reasons, such as gas phase nucleation phenomenon or peelings from the inner walls of reactor. For illustrating the cause of particles and their influence to the electrical property of the barrier layer, a conventional deposition process of forming a barrier layer is shown as an example here.
Please refer to FIG. 1 and FIG. 2. FIG. 1 and FIG. 2 are schematic diagrams illustrating a conventional method of forming a barrier layer. As shown in FIG. 1, first a substrate 10 having at least a stacked gate structure 12 thereon is provided. The stacked gate structure 12 has a spacer 14 disposed along the sidewalls of the stacked gate structure 12. The substrate 10 further includes a drain doped region 16 and the source doped region 18 on both sides of the stacked gate structure 12. Then a dielectric layer 20 is formed on the substrate 10, and a photoresist pattern (not shown) is employed as a hard mask to remove a portion of the dielectric layer 20 positioned on the drain doped region 16 for forming a plug hole 22.
As shown in FIG. 2, a CVD process is performed to form a barrier layer 24 on the inner walls of the plug hole 22. The barrier layer 24 is generally composed of Ti/TiN for enhancing the ohmic contact ability toward a bit line plug (not shown), which will be formed later. In addition, the barrier layer 24 is able to restrain metal atoms from diffusing. As described earlier, as long as the particles fall from the inner walls of the reactor or the gas phase nucleation phenomenon happens in the CVD process, particles 26 appear on the surface of the barrier layer 24.
Normally, an electrical property examination procedure is executed after interconnect processes. Those semiconductor components that fail to pass the examination procedure always include more particles than other wafers. Since those semiconductor components are not serviceable, to discard them seems to be the only solution. This seriously affects the production yield. Therefore, how to reduce the damage of particles is a key topic for study in the semiconductor industry.